fix(hex8): isolate AVX2 packet code from baseline COMDATs

src/fesa/elements/hex8_pair_simd.h

@@ -1,28 +1,60 @@
 #ifndef FESA_SRC_FESA_ELEMENTS_HEX8_PAIR_SIMD_H_
 #define FESA_SRC_FESA_ELEMENTS_HEX8_PAIR_SIMD_H_
 
-#include <array>
-
-#include "../math/high_low_arithmetic.h"
+#include <cstdint>
 
 namespace fesa::hex8_internal {
-using PairPacket = std::array<math_internal::HighLow, 4>;
+/// @brief Trivial raw carrier; neither component is normalized or rounded here.
+struct PacketPair {
+  double high;
+  double low;
+};
+/// @brief Four independent lanes with no executable constructor or operator.
+struct PairPacket {
+  PacketPair values[4];
+};
 struct MaterialPacketInput {
-  PairPacket deviatoric_left, deviatoric_right;
-  PairPacket shear_left, shear_right;
-  PairPacket tensor_left, gradient_dot;
+  PairPacket deviatoric_left;
+  PairPacket deviatoric_right;
+  PairPacket shear_left;
+  PairPacket shear_right;
+  PairPacket tensor_left;
+  PairPacket gradient_dot;
   PairPacket accumulated;
-  math_internal::HighLow weight;
+  PacketPair weight;
 };
 using MaterialPacketEvaluator = void (*)(const MaterialPacketInput&, PairPacket*);
 
+/// @brief Evaluates each lane's original checked material graph in order 0..3.
+/// @note Invalid arithmetic remains a raw invalid pair for the caller's gates.
 void EvaluateMaterialPacketScalar(const MaterialPacketInput& input,
                                   PairPacket* output);
+/// @brief Evaluates independent material lanes with the checked vector graph.
+/// @pre The selector has admitted the CPU/OS ISA and current masked FP state.
+/// @note No lane reduction or model failure is introduced; special packets bridge
+/// to original scalar arithmetic, preserving components and operation order.
 void EvaluateMaterialPacketAvx2(const MaterialPacketInput& input,
                                 PairPacket* output);
+/// @brief Baseline-ISA checked addition bridge in lane order 0..3.
+/// @note pair_shortcuts chooses the original local AddPair or general Add graph;
+/// invalid pairs are preserved, with no FP-state mutation or normalization here.
+void ScalarPacketAdd(const PairPacket& left, const PairPacket& right,
+                     bool pair_shortcuts, PairPacket* output);
+/// @brief Baseline-ISA original checked MultiplyPair bridge in lane order 0..3.
+/// @note Raw invalid outputs remain invalid; no component is rounded away.
+void ScalarPacketMultiply(const PairPacket& left, const PairPacket& right,
+                          PairPacket* output);
+/// @brief Baseline-ISA original checked TwoProduct bridge in lane order 0..3.
+/// @note Keeps finite/zero/underflow/FMA checks and the caller's FP state.
+void ScalarPacketTwoProduct(const double left[4], const double right[4],
+                            PairPacket* output);
 /// @brief Selects a private backend from CPU/OS and this thread's FP state.
 /// @note Never mutates FP state or caches a thread's environment decision.
 MaterialPacketEvaluator SelectMaterialPacketEvaluator();
+/// @brief Pure instruction/OS-state predicate; does not execute ISA probes.
+bool SupportsMaterialPacketInstructions(std::uint32_t leaf1_ecx,
+                                        std::uint64_t xcr0,
+                                        std::uint32_t leaf7_ebx);
 }  // namespace fesa::hex8_internal
 
 #endif  // FESA_SRC_FESA_ELEMENTS_HEX8_PAIR_SIMD_H_