KOKO\Mimi
85 lines
4.0 KiB
C++
85 lines
4.0 KiB
C++
#ifndef FESA_SRC_FESA_ELEMENTS_HEX8_PAIR_SIMD_H_
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#define FESA_SRC_FESA_ELEMENTS_HEX8_PAIR_SIMD_H_
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#include <cstdint>
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namespace fesa::hex8_internal {
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/// @brief Trivial raw carrier; neither component is normalized or rounded here.
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struct PacketPair {
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double high;
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double low;
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};
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/// @brief Four independent lanes with no executable constructor or operator.
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struct PairPacket {
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PacketPair values[4];
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};
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struct MaterialPacketInput {
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PairPacket deviatoric_left;
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PairPacket deviatoric_right;
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PairPacket shear_left;
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PairPacket shear_right;
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PairPacket tensor_left;
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PairPacket gradient_dot;
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PairPacket accumulated;
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PacketPair weight;
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};
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/// @brief One owned trial point/a and four independent b gradients, raw only.
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struct GeometryPacketInput {
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PacketPair gradient_a[3];
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PacketPair gradient_stress[3][3];
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PairPacket gradient_b[3];
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PacketPair weight;
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};
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/// @brief Independent raw contractions; accumulator entries remain caller-owned.
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struct GeometryPacketOutput {
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PairPacket gradient_dot;
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PairPacket weighted_geometric;
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};
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using GeometryPacketEvaluator = void (*)(const GeometryPacketInput&,
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GeometryPacketOutput*);
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/// @brief Baseline checked zero-start Dot3/ordered j,l Geo9 and weight products.
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/// @note Lane order is 0..3. Invalid pairs remain invalid for original gates.
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void EvaluateGeometryPacketScalar(const GeometryPacketInput& input,
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GeometryPacketOutput* output);
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/// @brief Evaluates independent b lanes without horizontal reduction.
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/// @pre The material selector has admitted CPU/OS/current masked FP state.
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/// @note Keeps original zero-start, product association and j,l Add order.
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void EvaluateGeometryPacketAvx2(const GeometryPacketInput& input,
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GeometryPacketOutput* output);
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using MaterialPacketEvaluator = void (*)(const MaterialPacketInput&, PairPacket*);
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/// @brief Evaluates each lane's original checked material graph in order 0..3.
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/// @note Invalid arithmetic remains a raw invalid pair for the caller's gates.
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void EvaluateMaterialPacketScalar(const MaterialPacketInput& input,
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PairPacket* output);
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/// @brief Evaluates independent material lanes with the checked vector graph.
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/// @pre The selector has admitted the CPU/OS ISA and current masked FP state.
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/// @note No lane reduction or model failure is introduced; special packets bridge
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/// to original scalar arithmetic, preserving components and operation order.
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void EvaluateMaterialPacketAvx2(const MaterialPacketInput& input,
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PairPacket* output);
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/// @brief Baseline-ISA checked addition bridge in lane order 0..3.
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/// @note pair_shortcuts chooses the original local AddPair or general Add graph;
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/// invalid pairs are preserved, with no FP-state mutation or normalization here.
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void ScalarPacketAdd(const PairPacket& left, const PairPacket& right,
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bool pair_shortcuts, PairPacket* output);
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/// @brief Baseline-ISA original checked MultiplyPair bridge in lane order 0..3.
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/// @note Raw invalid outputs remain invalid; no component is rounded away.
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void ScalarPacketMultiply(const PairPacket& left, const PairPacket& right,
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PairPacket* output);
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/// @brief Baseline-ISA original checked TwoProduct bridge in lane order 0..3.
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/// @note Keeps finite/zero/underflow/FMA checks and the caller's FP state.
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void ScalarPacketTwoProduct(const double left[4], const double right[4],
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PairPacket* output);
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/// @brief Selects a private backend from CPU/OS and this thread's FP state.
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/// @note Never mutates FP state or caches a thread's environment decision.
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MaterialPacketEvaluator SelectMaterialPacketEvaluator();
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/// @brief Pure instruction/OS-state predicate; does not execute ISA probes.
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bool SupportsMaterialPacketInstructions(std::uint32_t leaf1_ecx,
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std::uint64_t xcr0,
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std::uint32_t leaf7_ebx);
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} // namespace fesa::hex8_internal
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#endif // FESA_SRC_FESA_ELEMENTS_HEX8_PAIR_SIMD_H_
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